CY7C1518AV18_11 Datasheet, PDF (5/29 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM Two-Word Burst Architecture

CY7C1518AV18
CY7C1520AV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ_[x:0]
LD
I/O-
synchronous
Input-
synchronous
Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q_[x:0] are automatically tristated.
CY7C1518AV18  DQ_[17:0]
CY7C1520AV18  DQ_[35:0]
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data.
BWS₀,
BWS₁,
BWS₂,
BWS₃
Input-
synchronous
Byte write select 0, 1, 2, and 3  Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1518AV18 BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
CY7C1520AV18 BWS₀ controls D_[8:0], BWS₁ controls D_[17:9], BWS₂ controls D_[26:18] and BWS₃ controls
D_[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A, A0
Input-
synchronous
Address inputs. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4 M × 18 (2 arrays each of 2 M × 18) for CY7C1518AV18, and 2 M × 36 (2 arrays
each of 1 M × 36) for CY7C1520AV18.
CY7C1518AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
22 address inputs are needed to access the entire memory array.
CY7C1520AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
R/W
Input- Synchronous read or write input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
C
Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See application example for further details.
C
Input clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
K
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q_[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q_[x:0] when in single clock mode.
CQ
Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
CQ
Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the AC Timing table.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL turn off  Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this datasheet. For normal operation, this pin
can be connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR-I timing.
Document Number: 001-06982 Rev. *I
Page 5 of 29
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