CY7C1518AV18_11 Datasheet, PDF (21/29 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM Two-Word Burst Architecture

CY7C1518AV18
CY7C1520AV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
C_IN
C_CLK
C_O
Input capacitance
Clock input capacitance
Output capacitance
Test Conditions
T_A = 25 °C, f = 1 MHz, V_DD = 1.8 V, V_DDQ = 1.5 V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
_JA
Thermal resistance
(junction to ambient)
_JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA / JESD51.
Figure 4. AC Test Loads and Waveforms
Max
Unit
5.5
pF
8.5
pF
6
pF
165-ball FBGA
Package
Unit
16.3
°C/W
2.1
°C/W
V_REF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75 V
Z₀ = 50 
RQ =
250 
V_REF
R_L = 50 
V_REF = 0.75 V
OUTPUT
Device
Under
Test ^ZQ
INCLUDING
JIG AND
SCOPE
V_REF = 0.75 V
0.75 V
R = 50 
RQ =
250 
(b)
5 pF ^{0.25 V}
ALL INPUT PULSES^[25]
1.25 V
0.75 V
Slew Rate = 2 V/ns
Note
25.
Unless otherwise noted, test conditions assume
levels of 0.25 V to 1.25 V, and output loading of
signal transition time of 2 V/ns, timing reference levels
the specified I_OL / I_OH and load capacitance shown in
(oaf)0o.7f ^5FiVg,uVreRE4^F.
=
0.75
V,
RQ
=
250
,
V_DDQ
=
1.5
V,
input
pulse
Document Number: 001-06982 Rev. *I
Page 21 of 29
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