CY14B101LA_1107 Datasheet, PDF (5/28 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM

CY14B101LA
CY14B101NA
Pin Definitions
Pin Name I/O Type
Description
A₀–A₁₆
A₀–A₁₅
DQ₀–DQ₇
DQ₀–DQ₁₅
WE
Input
Input/Output
Input
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
BHE
BLE
V_SS
V_CC
HSB^[13]
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ₁₅–DQ₈.
Byte Low Enable, Active LOW. Controls DQ₇–DQ₀.
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (t_HHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
V_CAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No connect No connect. This pin is not connected to the die.
Note
13. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document #: 001-42879 Rev. *L
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