CY14B101LA_1107 Datasheet, PDF (3/28 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM

CY14B101LA
CY14B101NA
Pinouts
Figure 1. Pin Diagram – 44-pin TSOP II
NC
NC^[7]
A₀
A₁
A₂
A₃
A₄
CE
DQ₀
DQ₁
V_CC
V_SS
DQ₂
DQ₃
WE
A₅
A₆
A₇
A₈
A₉
NC
NC
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9 44-pin TSOP II 36
10
(× 8)
35
11
12
13
Top View
(not to scale)
34
33
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
HSB
NC
NNCC^[[65]]
NC^[4]
A₁₆
A₁₅
OE
DQ₇
DQ₆
V_SS
V_CC
DQ₅
DQ₄
V_CAP
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
NC
NC
A_{0 1}
44
A₁ 2
43
A₂ 3
42
A_{3 4}
41
A_{4 5}
40
CE 6
39
DQ_{0 7}
38
DQ₁ 8
37
DQ₂ 9 44-pin TSOP II 36
DQ₃ 10
(× 16)^[8]
35
V_CC
V_SS
DQ₄
11
12
13
Top View
(not to scale)
34
33
32
DQ₅ 14
31
DQ₆ 15
30
DQ₇ 16
29
WE ¹⁷
28
A₅ 18
27
A_{6 19}
26
A_{7 20}
25
A₈ 21
24
A₉ 22
23
Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC
V_{CAP 1}
48
A_{16 2}
47
A_{14 3}
46
A_{12 4}
45
A_{7 5}
44
A_{6 6}
43
A_{5 7}
42
NC ₈
41
A₄
NC
9
10
48-pin SSOP
40
39
NC 11
(×8)
38
NC
V_SS
NC
12 _{Top View} 37
13 _{(not to scale)} 36
14
35
NC 15
34
DQ0 16
33
A_{3 17}
32
A_{2 18}
31
A_{1 19}
30
A_{0 20}
29
DQ1 ₂₁
28
DQ2 ₂₂
27
NC 23
26
NC 24
25
V_CC
A₁₅
HSB
WE
A₁₃
A₈
A₉
NC
A₁₁
NC
NC
NC
V_SS
NC
NC
DQ6
OE
A₁₀
CE
DQ7
DQ5
DQ4
DQ3
V_CC
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. HSB pin is not available in 44-pin TSOP II (× 16) package.
32-pin SOIC
((x×88))
Top View
(not to scale)
NC ^[5]
NC ^[4]
A₁₅
OE
BHE
BLE
DQ₁₅
DQ₁₄
DQ₁₃
DQ₁₂
V_SS
V_CC
DQ₁₁
DQ₁₀
DQ₉
DQ₈
V_CAP
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
Document #: 001-42879 Rev. *L
Page 3 of 28
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