CY14B101LA_1107 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM

CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and RECALL cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20% to –10% operation
■ Industrial temperature
Logic Block Diagram ^{[1, 2, 3]}
■ Packages
❐ 32-pin small-outline integrated circuit (SOIC)
❐ 44-/54-pin thin small outline package (TSOP) Type II
❐ 48-pin shrink small-outline package (SSOP)
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Quatrum Trap
V_CC
V_CAP
1024 X 1024
A₅
R
O
A₆
W
STORE
POWER
CONTROL
A₇
A₈
A₉
A₁₂
RECALL
D
E
C
STATIC RAM
STORE/RECALL
CONTROL
HSB
A₁₃
O
ARRAY
A₁₄
A₁₅
A₁₆
D
1024 X 1024
E
R
SOFTWARE
DETECT
A₁₄ - A₂
DQ₀
DQ₁
DQ₂
DQ₃
DQ₄
DQ₅
DQ₆
DQ₇
DQ₈
DQ₉
DQ₁₀
DQ₁₁
DQ₁₂
DQ₁₃
DQ₁₄
DQ₁₅
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A₀ A₁ A₂ A₃ A₄ A₁₀ A₁₁
OE
WE
CE
BLE
BHE
Notes
1. Address A₀–A₁₆ for × 8 configuration and Address A₀–A₁₅ for × 16 configuration.
2. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-42879 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 14, 2011
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