S25FL064P Datasheet, PDF (48/62 Pages) SPANSION – 64-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

S25FL064P
11. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on V_CC, and must not
be driven low to select the device until V_CC reaches the allowable values as follows (see Figure 11.1 and Table 11.1 on page 49):
 At power-up, V_CC (min.) plus a period of t_PU
 At power-down, GND
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Read, Write Registers, program, or erase command should be sent to the device until V_CC rises to the V_CC min., plus a delay of
t_PU. At power-up, the device is in standby mode (not Deep Power-Down mode) and the WEL bit is reset (0).
Each device in the host system should have the V_CC rail decoupled by a suitable capacitor close to the package pins (this capacitor
is generally of the order of 0.1 µF), as a precaution to stabilizing the V_CC feed.
When V_CC drops from the operating voltage to below the minimum V_CC threshold at power-down, all operations are disabled and the
device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Registers,
program, or erase operation is in progress.
Figure 11.1 Power-Up Timing Diagram
Vcc
Vcc^(max)
Vcc^(min)
t PU
Full Device Access
Time
Figure 11.2 Power-down and Voltage Drop
Document Number: 002-00649 Rev. *I
Page 48 of 62