S34ML01G2 Datasheet, PDF (47/76 Pages) Cypress Semiconductor – 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded

S34ML01G2
S34ML02G2
S34ML04G2
Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol)
Cycle Type
DQx
CMD ADDR ADDR ADDR ADDR ADDR
DIN DIN DIN DIN
tADL
80h C1A C2A R1A R2A R3A
D0A D1A ^...
DnA
SR[6]
CMD
11h
tADL
tIPBSY
A
Cycle Type
DQx
CMD ADDR ADDR ADDR ADDR ADDR
DIN DIN DIN
tADL
80h C1B C2B R1B R2B R3B
D0B D1B
...
DIN
DnB
SR[6]
CMD
10h
tADL
tPROG
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. D0A-DnA Data to program for page A.
4. C1B-C2B Column address for page B. C1B is the least significant byte.
5. R1B-R3B Row address for page B. R1B is the least significant byte.
6. D0B-DnB Data to program for page B.
7. The block address bits must be the same except for the bit(s) that select the plane.
6.14 Block Erase Operation
Figure 6.15 Block Erase Operation (Erase One Block)
CLE
CE#
tWC
WE#
tWB
ALE
RE#
I/Ox
R/B#
60h Row Add1 Row Add2 Row Add3 D0h
Row Address
Auto Block Erase
Setup Command
Erase Command
tBERS
BUSY
tWHR
70h
I/O0
Read Status ^{I/O0=0 Successful Erase}
Command I/O0=1 Error in Erase
= Don’t Care
Document Number: 002-00499 Rev. *N
Page 47 of 76