CY7C63722C Datasheet, PDF (47/53 Pages) Cypress Semiconductor – enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller

CY7C63722C
CY7C63723C
CY7C63743C
Figure 49. SPI Master Timing, CPHA = 1
SS
(SS is under firmware control in SPI Master mode)
SCK (CPOL=0)
SCK (CPOL=1)
T_MDO1
MOSI
T_SCKH
T_SCKL
T_MDO
MSB
LS_DB ^esigns
r ^{New MISO}
MSB
T_MSU T_MHD
LSB
Figure 50. SPI Slave Timing, CPHA = 1
ed ^fo _SS
nd _TSSS
e _{SCK (CPOL=0)}
omm ^{SCK (CPOL=1)}
T_SCKH
T_SCKL
ec _MOSI
MSB
LSB
Not ^{R TSDO1}
T_SSU T_SHD
T_SDO
T_SSH
MISO
MSB
LSB
Document #: 38-08022 Rev. *D
Page 47 of 53
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