CY7C63722C Datasheet, PDF (34/53 Pages) Cypress Semiconductor – enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller

CY7C63722C
CY7C63723C
CY7C63743C
Figure 40. Port 1 Interrupt Polarity Register
(Address 0x07)
Bit [7:0]: P1[7:0] Interrupt Polarity
1 = Rising GPIO edge
Bit #
76543210
0 = Falling GPIO edge
Bit Name
P1 Interrupt Polarity
Read/Write W W W W W W W W
Reset
00000000
ns _{Figure 41. GPIO Interrupt Diagram}
w ^Desig _GPIO
e _Pin
Port Bit Interrupt
Polarity Register
M
U
X
OR Gate
(1 input per
GPIO pin)
GPIO Interrupt
Flip Flop
1D Q
CLR
r ^N _{1 = Enable}
fo ^{0 = Disable}
Not ^{Recommended IRA}
Port Bit Interrupt
Enable Register
1 = Enable
0 = Disable
Global
GPIO Interrupt
Enable
(Bit 6, Register 0x20)
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
Document #: 38-08022 Rev. *D
Page 34 of 53
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