CYRF69213_13 Datasheet, PDF (46/86 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, making its functionality independent of system clock speed.
SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
Figure 14. SPI Block Diagram
Register Block
SCK Speed Sel
SCK Clock Generation
Master/Slave Sel
SCK Clock Select
SCK_OE
SCK Polarity
SCK Phase
Little Endian Sel ^LE_SEL
SCK Clock Phase/Polarity
Select
SCK
SPI State Machine
SS_N
Data (8 bit)
Load
Empty
SCK
LE_SEL
Output Shift Buffer
Master/Slave Set
Shift Buffer
GPIO Block
SS_N
SS_N_OE
MISO_OE
MISO/MOSI
Crossbar
MOSI_OE
SCK
SS_N
MISO
Data (8 bit)
Load
Full
Input Shift Buffer
MOSI
Sclk Output Enable
Slave Select Output Enable
Master IN, Slave Out OE
Master Out, Slave In, OE
SCK_OE
SS_N_OE
MISO_OE
MOSI_OE
Document Number: 001-07552 Rev. *H
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