CYRF69213_13 Datasheet, PDF (43/86 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Table 53. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved Int Enable Int Act Low
Reserved
5K pull up
enable
Output
Enable
Read/Write
R/W
R/W
R/W
–
–
–
–
R/W
Default
0
0
0
0
0
0
0
0
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as a
GPIO pin which is pulled up. See Table 81 for information on enabling USB. When USB is enabled, none of the controls in this
register have any effect on the P1.0 pin
Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high
Bit 1
5K Pull up Enable
0 = Disable the 5 Kohm pull up resistors
1 = Enable 5 Kohm pull up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as pulled up
GPIOs
Bit 0This bit enables the output on P1.0/D+. This bit should be cleared in sleep mode.
Table 54. P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved Int Enable Int Act Low
Reserved
Open Drain Reserved
Output
Enable
Read/Write
–
R/W
R/W
–
–
R/W
–
R/W
Default
0
0
0
0
0
0
0
0
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as a
GPIO. See Table 81 for information on enabling USB. When USB is enabled, none of the controls in this register have any effect
on the P1.1 pin. When USB is disabled, the 5 Kohm pull up resistor on this pin can be enabled by the 5K Pull up Enable bit of the
P10CR Register (Table 53)
Bit 0This bit enables the output on P1.1/D-. This bit should be cleared in sleep mode.
Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at V_OL3
Table 55. P1.2 Configuration (P12CR) [0x0F] [R/W]
Bit #
7
6
5
4
3
Field
CLK Output Int Enable Int Act Low
TTL
Reserved
Threshold
Read/Write
R/W
R/W
R/W
R/W
–
Default
0
0
0
0
0
This register controls the operation of the P1.2
Bit 7
CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
2
Open Drain
R/W
0
1
Pull up
Enable
R/W
0
0
Output
Enable
R/W
0
Document Number: 001-07552 Rev. *H
Page 43 of 86