CYW20715 Datasheet, PDF (42/47 Pages) Cypress Semiconductor – Bluetooth 4.0 + EDR compliant

CYW20715
9.2.4 BSC Interface Timing
Table 25. BSC Interface Timing Specifications
Reference
Characteristics
1
Clock frequency
2
START condition setup time
3
START condition hold time
4
Clock low time
5
Clock high time
6
Data input hold time^a
7
Data input setup time
8
STOP condition setup time
9
Output valid from clock
10
Bus free time^b
Minimum
Maximum
Unit
100
–
400
800
kHz
1000
650
–
ns
280
–
ns
650
–
ns
280
–
ns
0
–
ns
100
–
ns
280
–
ns
–
400
ns
650
–
ns
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions
b. Time that the cbus must be free before a new transaction can start.
Figure 16. BSC Interface Timing Diagram
SCL
2
SDA
IN
SDA
OUT
1
5
3
4
67
9
8
10
Document Number: 002-14813 Rev. *B
Page 42 of 47