CYW20715 Datasheet, PDF (18/47 Pages) Cypress Semiconductor – Bluetooth 4.0 + EDR compliant

CYW20715
5.1.2 Slot Mapping
The device supports up to three simultaneous, full-duplex SCO or eSCO channels. These channels are time-multiplexed onto the
PCM interface using a time slotting scheme based on the audio sampling rate, as described in Table 2.
Table 2. PCM Interface Time Slotting Scheme
Audio Sample Rate
8 kHz
16 kHz
Time Slotting Scheme
The number of slots depends on the selected interface rate, as follows:
Interface rate Slot
128
1
256
2
512
4
1024
8
2048
16
The number of slots depends on the selected interface rate, as follows:
Interface rate Slot
256
1
512
2
1024
4
2048
8
Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tri-states its
output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tri-states its output
after the falling edge of the PCM clock during the last bit of the slot.
5.1.3 Wideband Speech
The CYW20715 provides support for Wideband Speech (WBS) in two ways:
■ Transparent mode
The host encodes WBS packets and the encoded packets are transferred over the
PCM bus for SCO or eSCO voice connections. In Transparent mode, the PCM bus is
typically configured in master mode for a 4 kHz sync rate with 16-bit samples, resulting
in a 64 kbps bit rate.
■ On-chip SmartAudio® technology
The CYW20715 can perform Subband-Codec (SBC) encoding and decoding of linear
16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus.
5.1.4 Frame Synchronization
The device supports both short and long frame synchronization types in both master and slave configurations. In short frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the 8 kHz audio frame rate (which is a single bit period in
width) and synchronized to the rising edge of the bit clock. The PCM slave expects PCM_SYNC to be high on the falling edge of the
bit clock and the first bit of the first slot to start at the next rising edge of the clock. In the long frame synchronization mode, the frame
synchronization signal is an active-high pulse at the 8 kHz audio frame rate. However, the duration is 3-bit periods and the pulse starts
coincident with the first bit of the first slot.
5.1.5 Data Formatting
The device can be configured to generate and accept several different data formats. The device uses 13 of the 16 bits in each PCM
frame. The location and order of these 13 bits is configurable to support various data formats on the PCM interface. The remaining
three bits are ignored on the input, and may be filled with zeros, ones, a sign bit, or a programmed value on the output. The default
format is 13-bit two’s complement data, left justified, and clocked most significant bit first.
Document Number: 002-14813 Rev. *B
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