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CY8C24123A_12 Datasheet, PDF (41/65 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip | |||
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CY8C24123A
CY8C24223A
CY8C24423A
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and â40 °C ï£ TA ï£ 85 °C, 3.0 V to 3.6 V and â40 °C ï£ TA ï£ 85 °C, or 2.4 V to 3.0 V and â40 °C ï£ TA ï£ 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 37. 5-V and 3.3-V AC Digital Block Specifications
Function
Description
Min Typ
All functions Block input clock frequency
Timer
VDD ï³ 4.75 V
VDD < 4.75 V
Input clock frequency
â
â
â
â
No capture, VDD ï³ï 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
â
â
â
â
â
â
50[25]
â
Counter
Input clock frequency
No enable input, VDD ï³ 4.75 V
â
â
No enable input, VDD < 4.75 V
â
â
With enable input
â
â
Enable input pulse width
50[25]
â
Dead Band Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
20
â
50[25]
â
50[25]
â
Input clock frequency
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
VDD ï³ 4.75 V
VDD < 4.75 V
Input clock frequency
VDD ï³ 4.75 V
VDD < 4.75 V
Input clock frequency
â
â
â
â
â
â
â
â
â
â
SPIM
Input clock frequency
â
â
SPIS
Input clock (SCLK) frequency
â
â
Width of SS_negated between 50[25] â
transmissions
Transmitter Input clock frequency
Receiver
VDD ï³ 4.75 V, 2 stop bits
VDD ï³ 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
â
â
â
â
â
â
VDD ï³ 4.75 V, 2 stop bits
VDD ï³ 4.75 V, 1 stop bit
VDD < 4.75 V
â
â
â
â
â
â
Max
49.2
24.6
49.2
24.6
24.6
â
49.2
24.6
24.6
â
â
â
â
49.2
24.6
49.2
24.6
24.6
8.2
4.1
â
49.2
24.6
24.6
49.2
24.6
24.6
Unit
MHz
MHz
MHz
MHz
MHz
ns
MHz
MHz
MHz
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Notes
MHz
MHz
ns
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
MHz
MHz
MHz
MHz
MHz
MHz
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
Note
25. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12028 Rev. *R
Page 41 of 65
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