CY8C24123A_12 Datasheet, PDF (39/65 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip

CY8C24123A
CY8C24223A
CY8C24423A
Table 35. 2.7-V AC Operational Amplifier Specifications
Symbol
t_ROA
t_SOA
SR_ROA
SR_FOA
BW_OA
E_NOA
Description
Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Noise at 1 kHz (Power = medium, Opamp bias = high)
Min
Typ
Max
Units
–
–
3.92
µs
–
–
0.72
µs
–
–
5.41
µs
–
–
0.72
µs
0.31
–
2.7
–
–
V/µs
–
V/µs
0.24
–
1.8
–
–
V/µs
–
V/µs
0.67
–
2.8
–
–
100
–
MHz
–
MHz
–
nV/rt-Hz
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor.
Figure 13. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz) 1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry.
At high frequencies, increased power level reduces the noise spectrum level.
Document Number: 38-12028 Rev. *R
Page 39 of 65