Z9953 Datasheet, PDF (4/6 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9953
3.3V, 180MHz, Multi-Output Zero Delay Buffer
AC Parameters¹
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Tr / Tf
TCLK Input Rise / Fall
Fref
Reference Input Frequency²
25
3.0
ns
110
MHz
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
500
MHz
Tlock
Maximum PLL lock Time
Tr / Tf Output Clocks Rise / Fall Time^4,5
0.10
10
ms
1.0
ns
Fout
Maximum Output Frequency
50
110
MHz
25
62.5
FoutDC
Output Duty Cycle^4,5
200
45
50
55
%
TCCJ
Cycle to Cycle Jitter (peak to
peak)^4,5
TSKEW Any Output to Any Output Skew^4,5
-
100
ps
-
250
ps
Tpd
Input to FB_IN Delay (PLL
-75
-
125
ps
locked)^3,4,5
tpZL,
tpZH
Output enable time (all outputs)
6
ns
tpLZ,
tpHZ
Output disable time (all outputs)
7
ns
Tpd
Input to Q Delay (PLL bypassed)
3
7
ns
VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd (PLL locked) is input reference frequency dependent.
Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines.
Note 5: Outputs loaded with 30pF each
CONDITIONS
0.8V to 2.0V
VCO_SEL = ‘0’
VCO_SEL = ‘1’
Bypass Mode
Description
The Z9953 is a PLL based clock generator that provides low skew and low jitter clock outputs for high performance
systems. The Z9953 features a differential PLL to minimize cycle-to-cycle and phase jitter. The PLL is
ensured stable operation given that the VCO is configured to run between 200MHz and 500MHz.
The input reference is a differential LVPECL clock. All other control inputs are LVCMOS/LVTTL compatible
The Z9953 features 9 LVCMOS/LVTTL compatible outputs each capable of driving two series terminated 50Ω
transmission lines. With this capability the Z9953 has an effective fan-out of 1:18. The outputs can also be tri-stated when
MR/OE# is set high.
When used as a zero-delay buffer any of the 9 outputs can be used as the feedback input to the PLL. The PLL works to
align the output edge with the input reference edge thus producing a near zero delay.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07086 Rev. *B
12/26/2002
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