Z9953 Datasheet, PDF (2/6 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9953
Pin Description
PIN
NAME
PWR
I/O
8
PECL_CLK
I
9
PECL_CLK#
I
12, 14, 16, Q(7:0)
VDDC
O
18, 20, 22,
24, 26
28
FB_OUT
VDDC
O
2
FB_IN
I
10
MR/OE#
I
30
PLL_EN
I
31
BYPASS#
I
32
VCO_SEL
I
11, 15, 19, VDDC
23, 27
1
VDD
7, 13, 17, 21, VSS
25, 29
3, 4, 5, 6
NC
PD = Internal Pull-Down, PU = Internal Pull-Up.
3.3V, 180MHz, Multi-Output Zero Delay Buffer
PECL Input Clock.
PECL Input Clock.
Clock Output.
Description
Feedback Clock Output. Connect to FB_IN for normal
operation. A bypass delay capacitor at this output will
control Input Reference / Output phase relationships.
Feedback Clock Input. Connect to FB_OUT for accessing
the PLL.
Master Reset/Output Enable Input. When asserted high,
resets all of the internal flip-flops and also disables all of the
outputs. When pulled low, releases the internal flip-flops
from reset and enables all of the outputs.
PLL Select Input. When asserted high, VCO output is
selected. And when set low, PECL_CLK is the input to the
output dividers.
PLL Enable Input. When high, PLL is enabled and when
low, PLL is bypassed.
VCO Divider Select Input. When set high, VCO output is
divided by 2. When set low, the divider is bypassed.
3.3V Power Supply for Output Clock Buffers.
3.3V Power Supply for PLL
Common Ground
No Connection
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07086 Rev. *B
12/26/2002
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