W40S01-04 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – SDRAM Buffer - 4 DIMM

W40S01-04
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 2 gives the bit formats for registers located in Data Bytes
0–6.
Table 2. Data Bytes 0–2 Serial Configuration Map^[2]
Affected Pin
Bit(s)
Pin No.
Pin Name
Control Function
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
18
SDRAM7 Clock Output Disable
6
17
SDRAM6 Clock Output Disable
5
14
SDRAM5 Clock Output Disable
4
13
SDRAM4 Clock Output Disable
3
9
SDRAM3 Clock Output Disable
2
8
SDRAM2 Clock Output Disable
1
5
SDRAM1 Clock Output Disable
0
4
SDRAM0 Clock Output Disable
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
45
SDRAM15 Clock Output Disable
6
44
SDRAM14 Clock Output Disable
5
41
SDRAM13 Clock Output Disable
4
40
SDRAM12 Clock Output Disable
3
36
SDRAM11 Clock Output Disable
2
35
SDRAM10 Clock Output Disable
1
32
SDRAM9 Clock Output Disable
0
31
SDRAM8 Clock Output Disable
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
28
SDRAM17 Clock Output Disable
6
21
SDRAM16 Clock Output Disable
5
N/A
Reserved (Reserved)
4
N/A
Reserved (Reserved)
3
N/A
Reserved (Reserved)
2
N/A
Reserved (Reserved)
1
N/A
Reserved (Reserved)
0
N/A
Reserved (Reserved)
Bit Control
0
1
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
--
--
--
--
--
--
--
--
--
--
--
--
Note:
2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
4