W40S01-04 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – SDRAM Buffer - 4 DIMM

W40S01-04
Pin Definitions
Pin Name
SDRAM0:17
BUF_IN
SDATA
SCLOCK
VDDQ3
GND
OE
NC
Pin
No.
4, 5, 8, 9,
13, 14, 17,
18, 21, 28,
31, 32, 35,
36, 40, 41,
44, 45
11
24
25
3, 7, 12, 16,
20, 23, 29,
33, 37, 42,
46
6, 10, 15,
19, 22, 26,
27, 30, 34,
39, 43
38
1, 2, 47, 48
Pin
Type
O
I
I/O
I
P
G
I
-
Pin Description
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled
to within ± 250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
I²C Data Input: Data should be presented to this input as described in the I²C section
of this data sheet. Internal 250-kΩ pull-up resistor.
I²C clock Input: The I²C data clock should be presented to this input as described in
the I²C section of this data sheet. Internal 250-kΩ pull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection: Connect all ground pins to the common system ground plane.
Output Enable: Internal 250-kΩ pull-up resistor. Three-states outputs when LOW.
No Connect: Do not connect.
2