W255H Datasheet, PDF (4/10 Pages) Cypress Semiconductor – 200-MPz 24-Output Buffer for 4DDR or 3 SDRAM DIMMS

W255
Maximum Ratings
Supply Voltage to Ground Potential ..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN) ............ –0.5V to V_DD+0.5
Operating Conditions ^[2]
Storage Temperature.................................. –65°C to +150°C
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015)
Parameter
VDD3.3
VDD2.5
T_A
C_OUT
C_IN
Description
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Min.
Typ.
Max.
Unit
3.135
3.465
V
2.375
2.625
V
0
70
°C
6
pF
5
pF
Electrical Characteristics Over the Operating Range
Parameter
V_IL
V_IH
I_IL
I_IH
I_OH
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
I_OL
V_OL
V_OH
I_DD
I_DD
I_DDS
V_OUT
Output LOW Current
Output LOW Voltage^[3]
Output HIGH Voltage^[3]
Supply Current^[3]
(DDR-only mode)
Supply Current
(DDR-only mode)
Supply Current
Output Voltage Swing
V_OC
Output Crossing Voltage
IN_DC
Input Clock Duty Cycle
Test Conditions
For all pins except SMBus
V_IN = 0V
V_IN = V_DD
V_DD = 2.375V
V_OUT = 1V
V_DD = 2.375V
V_OUT = 1.2V
I_OL = 12 mA, V_DD = 2.375V
I_OH = –12 mA, V_DD = 2.375V
Unloaded outputs, 133 MHz
Min.
2.0
–18
26
1.7
Loaded outputs, 133 MHz
PWR_DWN# = 0
See test circuity (refer to
Figure 1)
0.7
(V_DD/2)
–0.1
48
Typ.
Max.
0.8
50
50
–32
35
0.6
400
500
V_DD/2
100
V_DD +0.6
(V_DD/2)
+0.1
52
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
µA
V
V
%
Switching Characteristics ^[4]
Parameter
Name
Test Conditions
Min. Typ. Max. Unit
–
Operating Frequency
66
–
Duty Cycle^{[3, 5]} = t₂ ÷ t₁
Measured at 1.4V for 3.3V outputs
IN_DC
Measured at V_DD/2 for 2.5V outputs –5%
t₃
SDRAM Rising Edge Rate^[3]
Measured between 0.4V and 2.4V
1.0
t₄
SDRAM Falling Edge Rate^[3]
Measured between 2.4V and 0.4V
1.0
t_3d
DDR Rising Edge Rate^[3]
Measured between 20% to 80% of
0.5
output (refer to Figure 1)
200
IN_DC
+5%
2.75
2.75
1.50
MHz
%
V/ns
V/ns
V/ns
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Document #: 38-07255 Rev. *C
Page 4 of 10