W232_02 Datasheet, PDF (4/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer

W232
Absolute Maximum Ratings^[1]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
.
Parameter
Description
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
Unit
V_DD, V_IN
T_STG
T_A
T_B
P_D
Voltage on any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
–0.5 to +7.0
V
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
DC Electrical Characteristics: T_A = 0°C to 70°C, V_DD = 3.3V ±10%
Parameter
I_DD
V_IL
V_IH
V_OL
V_OH
I_IL
I_IH
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Test Condition
Unloaded, 100 MHz
I_OL = 12 mA
I_OH = –12 mA
V_IN = 0V
V_IN = V_DD
Min.
Typ.
Max.
Unit
200
mA
0.8
V
2.0
V
0.8
V
2.1
V
50
µA
50
µA
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f_OUT
Output Frequency
30-pF load^[5]
25
140
MHz
t_R
Output Rise Time
0.8V to 2.0V, 30-pF load
2.1
ns
t_F
tI_CLKR
tI_CLKF
t_PEJ
Output Fall Time
2.0V to 0.8V, 30-pF load
Input Clock Rise Time^[2]
Input Clock Fall Time^[2]
CLK to FBIN Skew Variation^{[3, 4]} Measured at V_DD/2
–350
0
2.5
ns
4.5
ns
4.5
ns
350
ps
t_SK
Output to Output Skew
All outputs loaded equally
–100
0
100
ps
t_D
Duty Cycle
30-pF load
43
50
58
%
t_LOCK
t_JC
PLL Lock Time
Jitter, Cycle-to-Cycle^[5]
Power supply stable
1.0
ms
150
ps
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Longer input rise and fall time will degrade skew and jitter performance.
3. Skew is measured at V_DD/2 on rising edges.
4. Duty cycle is measured at V_DD/2.
5. Production tests are run at 133 MHz.
6. For frequencies below 40 MHz, Cycle-to-Cycle Jitter degrades to 175 ps.
Ordering Information
Ordering Code
Option Number
W232
-09, -10
X = 24-pin TSSOP
Package Type
Document #: 38-07167 Rev. *B
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