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W232_02 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer
Features
• Well-suited to both 100- and 133-MHz designs
• Ten/eleven LVCMOS/LVTTL outputs
• 3.3V power supply
• Available in 24-pin TSSOP package
W232
Ten Output Zero Delay Buffer
Key Specifications
Operating Voltage: .............................................. 3.3V ± 10%
Operating Range: ........................25 MHz < fOUT < 140 MHz
Cycle-to-Cycle Jitter: ...............................................< 150 ps
Output to Output Skew: ...........................................< 100 ps
Phase Error Jitter: ....................................................< 125 ps
Static Phase Error: ...................................................< 150 ps
Block Diagram
Pin Configurations
FBIN
CLK
PLL
OE0:4
OE
OE5:8
FBOUT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Configuration of these blocks dependent upon specific option being used.
AGND
1
VDD
2
Q0
3
Q1
4
Q2
5
GND
6
GND
7
Q3
8
Q4
9
VDD
10
OE0:4
11
FBOUT
12
AGND
1
VDD
2
Q0
3
Q1
4
Q2
5
GND
6
GND
7
Q3
8
Q4
9
VDD
10
OE
11
FBOUT
12
24
CLK
23
AVDD
22
VDD
21
Q8
20
Q7
19
GND
18
GND
17
Q6
16
Q5
15
VDD
14
OE5:8
13
FBIN
24
CLK
23
AVDD
22
VDD
21
Q9
20
Q8
19
GND
18
GND
17
Q7
16
Q6
15
Q5
14
VDD
13
FBIN
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07167 Rev. *B
Revised December 15, 2002