W232_02 Datasheet, PDF (2/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer

W232
Pin Definitions
Pin
Name
Pin No.
(-09)
CLK
24
FBIN
13
Q0:8
FBOUT
3, 4, 5, 8,
9, 16, 17,
20, 21
12
AVDD
AGND
VDD
GND
OE0:4
OE
OE5:8
23
1
2, 10, 15,
22
6, 7, 18,
19
11
–
14
Pin No.
(-10)
24
13
3, 4, 5, 8,
9, 15, 16,
17, 20, 21
12
23
1
2, 10, 14
22
6, 7, 18,
19
–
11
–
Pin
Type
I
I
O
O
P
G
P
G
I
I
I
Pin Description
Reference Input: Output signals Q0:9 will be synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (typically
FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT
is equal in length to the traces between the outputs and the signal destina-
tions, then the signals received at the destinations will be synchronized to the
CLK signal input.
Outputs: The frequency and phase of the signals provided by these pins will
be equal to the reference signal if properly laid out.
Feedback Output: Typically this is connected directly to the FBIN input with
a trace equal in length to the traces between outputs Q0:9 and the destination
points of these output signals.
Analog Power Connection: Connect to 3.3V. Use ferrite beads to help
reduce noise for optimal jitter performance.
Analog Ground Connection: Connect to common system ground plane.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect to common system ground plane.
Output Enable Input: Tie to V_DD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.
Output Enable Input: Tie to V_DD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state.
Output Enable Input: Tie to V_DD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Overview
The W232 is a PLL-based clock driver designed for use in
systems requiring a large number of synchronous timing
signals. The clock driver has output frequencies of up to 140
MHz and output-to-output skews of less than 100 ps. The
W232 provides minimum cycle-to-cycle and long-term jitter,
which is of significant importance to meet the tight
input-to-input skew budget in DIMM applications.
The W232 was specifically designed to accept SSFTG signals
currently being used in motherboard designs to reduce EMI.
Zero delay buffers which are not designed to pass this feature
through may cause skewing failures.
Output enable pins allow for shutdown of output when they are
not being used. This reduces EMI and power consumption.
Document #: 38-07167 Rev. *B
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