W232-09XT Datasheet, PDF (4/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer

W232
Absolute Maximum Ratings^[1]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not
implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
V_DD, V_IN
T_STG
T_A
T_B
P_D
Description
Voltage on any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
Rating
Unit
–0.5 to +7.0
V
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
DC Electrical Characteristics: T_A = 0°C to 70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
I_DD
Supply Current
Unloaded, 100 MHz
V_IL
Input Low Voltage
V_IH
Input High Voltage
2.0
V_OL
Output Low Voltage I_OL = 12 mA
V_OH
Output High Voltage I_OH = –12 mA
2.1
I_IL
Input Low Current V_IN = 0V
I_IH
Input High Current V_IN = V_DD
200
mA
0.8
V
V
0.8
V
V
50
μA
50
μA
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
Min
Typ
f_OUT
Output Frequency
30-pF load^[5]
25
t_R
Output Rise Time
0.8V to 2.0V, 30-pF load
t_F
Output Fall Time
2.0V to 0.8V, 30-pF load
tI_CLKR
Input Clock Rise Time^[2]
tI_CLKF
Input Clock Fall Time^[2]
t_PEJ
CLK to FBIN Skew
Variation^{[3, 4]}
Measured at V_DD/2
–350
0
t_SK
Output to Output Skew All outputs loaded equally
–100
0
t_D
Duty Cycle
30-pF load
43
50
t_LOCK
PLL Lock Time
Power supply stable
t_JC
Jitter, Cycle-to-Cycle^[5]
Max
Unit
140
MHz
2.1
ns
2.5
ns
4.5
ns
4.5
ns
350
ps
100
ps
58
%
1.0
ms
150
ps
Notes
1. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Longer input rise and fall time degrades skew and jitter performance.
3. Skew is measured at V_DD/2 on rising edges.
4. Duty cycle is measured at V_DD/2.
5. Production tests are run at 133 MHz.
6. For frequencies below 40 MHz, Cycle-to-Cycle Jitter degrades to 175 ps.
Document #: 38-07167 Rev. *E
Page 4 of 6
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