W232-09XT Datasheet, PDF (3/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer

W232
VDD
VDD
Figure 3. Schematic
1 AGND
GND 24
2 VDD
0.1μ F
3 Q0
4 Q1
AVDD 23
VDD 22
0.1μ F
Q9 21
5 Q2
Q8 20
6 GND
GND 19
7 GND
GND 18
8 Q3
Q7 17
9 Q4
Q6 16
10 VDD
0.1μ F
11 OE
Q5 15
VDD 14
12 FBOUT FBIN 13
0.1μF ^{FB 3.3V}
10μ F
10μ F
FB
VDD
0.1μF
VDD
Spread Aware
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation (SSFTG).
Cypress has been one of the pioneers of SSFTG development,
and designed this product so as not to filter off the Spread
Spectrum (SS) feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew which
may cause problems in systems requiring synchronization.
For more details on SS timing technology, see the Cypress appli-
cation note titled, “EMI Suppression Techniques with Spread
Spectrum Frequency Timing Generator (SSFTG) ICs” - AN1278.
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. To achieve this, layout must
compensate for trace length between the ZDB and the target
devices. The method of compensation is as follows.
External feedback is the trait that allows this compensation.
Since the PLL on the ZDB causes the feedback signal to be in
phase with the reference signal, when laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the
input signal, this may also be affected by either making the trace
to the FBIN pin a little shorter or a little longer than the traces to
the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the
ability to synchronize signals up to the signal coming from some
other device. This implementation can be applied to any device
(ASIC, multiple output clock buffer/driver, and so on) which is put
into the feedback path.
As shown in Figure 4, if the traces between the ASIC/buffer and
the destination of the clock signal(s) (A) are equal in length to the
trace between the buffer and the FBIN pin, the signals at the
destination(s) device are driven HIGH at the same time the
Reference clock provided to the ZDB goes HIGH. Synchronizing
the other outputs of the ZDB to the outputs form the ASIC/Buffer
is, however, more complex as any propagation delay in the
ASIC/Buffer must be accounted for.
Figure 4. 6 Output Buffer in the Feedback Path
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Document #: 38-07167 Rev. *E
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