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W232-09XT Datasheet, PDF (1/6 Pages) Cypress Semiconductor – Ten Output Zero Delay Buffer
W232
Ten Output Zero Delay Buffer
Features
■ Well-Suited to both 100 and 133 MHz Designs
■ 10 or 11 LVCMOS/LVTTL Outputs
■ 3.3V Power Supply
■ Available in 24-Pin TSSOP Package
Key Specifications
■ Operating Voltage: 3.3V ± 10%
■ Operating Range: 25 MHz < fOUT < 140 MHz
■ Cycle-to-Cycle Jitter less than 150 ps
■ Output to Output Skew less than100 ps
■ Phase Error Jitter less than 125 ps
■ Static Phase Error: less than 150 ps
Logic Block Diagram
FBIN
CLK
PLL
OE0:4
OE
OE5:8
FBOUT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Configuration of these blocks dependent upon specific option being used.
Pinouts
Figure 1. 24-Pin TSSOP - W232-09
AGND
1
24
VDD
2
23
Q0
3
22
Q1
4
21
Q2
5
20
GND
6
19
GND
7
18
Q3
8
17
Q4
9
16
VDD
10
15
OE0:4
11
14
FBOUT
12
13
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
Figure 2. 24-Pin TSSOP - W232-10
AGND
1
24
VDD
2
23
Q0
3
22
Q1
4
21
Q2
5
20
GND
6
19
GND
7
18
Q3
8
17
Q4
9
16
VDD
10
15
OE
11
14
FBOUT
12
13
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07167 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 27, 2009
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