CYD01S18V Datasheet, PDF (4/26 Pages) Cypress Semiconductor – FLEx18™ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM

CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions
Left Port
Right Port
Description
A_0L–A_18L
BE_0L–BE_1L
BUSY_L[2,5]
C_L
CE0_L[10]
CE1_L[9]
DQ_0L–DQ_17L
OE_L
A_0R–A_18R
BE_0R–BE_1R
BUSY_R[2,5]
C_R
CE0_R[10]
CE1_R[9]
DQ_0R–DQ_17R
OE_R
Address Inputs.
Byte Enable Inputs. Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array.
Port Busy Output. When the collision is detected, a BUSY is asserted.
Input Clock Signal.
Active Low Chip Enable Input.
Active High Chip Enable Input.
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
INT_L
INT_R
Mailbox Interrupt Flag Output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INT_L is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPD_L[2,4]
LowSPD_R[2,4]
Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
PORTSTD[1:0]_L[2,4] PORTSTD[1:0]_R[2,4] Port Address/Control/Data I/O Standard Select Input.
R/W_L
R/W_R
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the
dual-port memory array.
READY_L[2,5]
READY_R[2,5]
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
CNT/MSK_L[9]
ADS_L[10]
CNTEN_L[10]
CNTRST_L[9]
CNTINT_L[11]
CNT/MSK_R[9]
ADS_R[10]
CNTEN_R[10]
CNTRST_R[9]
CNTINT_R[11]
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
WRP_L[2,3]
WRP_R[2,3]
Port Counter Wrap Input. After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
RET_L[2,3]
FTSEL_L[2,3]
VREF_L[2,4]
RET_R[2,3]
FTSEL_R[2,3]
VREF_R[2,4]
Port Counter Retransmit Input. Counter control input.
Flow-Through Mode Select Input.
Port External High-Speed IO Reference Input.
VDDIO_L
VDDIO_R
Port IO Power Supply.
REV_L[2,4]
REV_R[2,4]
Reserved pins for future features.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
TRST^[2,5]
JTAG Reset Input.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Document #: 38-06077 Rev. *C
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