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| CYD01S18V Datasheet, PDF (16/26 Pages) Cypress Semiconductor – FLEx18™ 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM | |||
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CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Bank Select Read[35, 36]
CLK
tSA
ADDRESS(B1)
tSC
CE(B1)
tCYC2
tCH2
tCL2
tHA
A0
A1
tHC
tCD2
A2
tSC tHC tCD2
DATAOUT(B1)
tSA
tHA
ADDRESS(B2)
A0
A1
CE(B2)
tSC
tHC
DATAOUT(B2)
Q0
tDC
A2
tSC
tHC
Read-to-Write-to-Read (OE = LOW)[34, 37, 38, 39, 40]
tCYC2
tCH2
tCL2
CLK
A3
tCKHZ
Q1
tDC
A3
tCD2
tCKLZ
A4
A5
tCD2
tCKLZ
A4
tCKHZ
Q3
A5
tCKHZ
Q2
tCD2
Q4
tCKLZ
CE
tSC
tHC
R/W
tSW
tHW
ADDRESS
An
tSA
tHA
DATAIN
DATAOUT
tSW
tHW
An+1
An+2
tCD2
tDC
Qn
An+2
tCKHZ
An+2
tSD tHD
Dn+2
An+3
READ
NO OPERATION
WRITE
Notes:
35. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
36. ADS = CNTEN= BE0 â BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
37. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
38. During âNo Operation,â data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
39. CE0 = OE = BE0 â BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
40. CE0 = BE0 â BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06077 Rev. *C
Page 16 of 26
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