CY14C512PA_13 Datasheet, PDF (4/42 Pages) Cypress Semiconductor – 512-Kbit (64 K x 8) SPI nvSRAM

CY14C512PA
CY14B512PA
CY14E512PA
Device Operation
CY14X512PA is a 512-Kbit serial (SPI) nvSRAM memory with
integrated RTC and SPI interface. All the reads and writes to
nvSRAM happen to the SRAM, which gives nvSRAM the unique
capability to handle infinite writes to the memory. The data in
SRAM is secured by a STORE sequence that transfers the data
in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (V_CAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
In CY14X512PA, the 512-Kbit memory array is organized as
64 K words × 8 bits. The memory can be accessed through a
standard SPI interface that enables very high clock speeds up to
40 MHz with zero cycle delay read and write cycles. This
nvSRAM chip also supports 104 MHz SPI access speed with a
special instruction for read operation. CY14X512PA supports
SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates
as SPI slave. The device is enabled using the Chip Select (CS)
pin and accessed through Serial Input (SI), Serial Output (SO),
and Serial Clock (SCK) pins.
CY14X512PA provides the feature for hardware and software
write protection through the WP pin and WRDI instruction.
CY14X512PA also provides mechanisms for block write
protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the
Status Register. Further, the HOLD pin is used to suspend any
serial communication without resetting the serial sequence.
CY14X512PA uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, CY14X512PA provides four special instructions that allow
access to four nvSRAM specific functions: STORE, RECALL,
AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14X512PA allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and two bytes of address. The data
is read out on the SO pin.
Speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, two bytes of address, and one dummy
byte. The data is read out on the SO pin.
CY14X512PA enables burst mode reads to be performed
through SPI. This enables reads on consecutive addresses
without issuing a new READ instruction. When the last address
in memory is reached in burst mode read, the address rolls over
to 0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the Memory Access
section of SPI Protocol Description
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The CY14X512PA STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X512PA is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V_CAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V_CC to
charge the capacitor connected to the V_CAP pin. When the
voltage on the V_CC pin drops below V_SWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V_CAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to V_CAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore Disable (ASDISB) Instruction on page 17). If
AutoStore is enabled without a capacitor on the V_CAP pin, the
device attempts an AutoStore operation without sufficient charge
Document Number: 001-65268 Rev. *F
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