CY14C512PA_13 Datasheet, PDF (33/42 Pages) Cypress Semiconductor – 512-Kbit (64 K x 8) SPI nvSRAM

CY14C512PA
CY14B512PA
CY14E512PA
RTC Characteristics
Over the Operating Range
Parameter
V_RTCbat
I_BAK[14]
RTC battery pin voltage
RTC backup current
Description
V_RTCcap[15]
RTC capacitor pin voltage
tOCS
V_BAKFAIL
V_DR
t_RTCp
R_BKCHG
RTC oscillator time to start
Backup failure threshold
BPF flag retention voltage
RTC processing time from end of ‘W’ bit set to ‘0’
RTC backup capacitor charge current limiting resistor
T_A (Min)
25 °C
T_A (Max)
T_A (Min)
25 °C
T_A (Max)
Min
Typ ^[13]
Max Units
1.8
3.0
3.6
V
–
–
0.45
µA
–
0.45
–
µA
–
–
0.60
µA
1.6
–
3.6
V
1.5
3.0
3.6
V
1.4
–
3.6
V
–
1
2
sec
1.8
–
2.2
V
1.6
–
–
V
–
–
1
ms
350
–
850

AC Switching Characteristics
Over the Operating Range
Parameters ^[16]
Cypress
Alt.
Parameter Parameter
Description
25 MHz
(RDRTC Instruction)
[17]
Min
Max
f_SCK
f_SCK
Clock frequency, SCK
–
25
t_CL[18]
t_WL
Clock pulse width LOW
18
–
t_CH[18]
t_WH
Clock pulse width HIGH
18
–
t_CS
t_CE
CS HIGH time
20
–
t_CSS
t_CES
CS setup time
10
–
t_CSH
t_CEH
CS hold time
10
–
t_SD
t_SU
Data in setup time
5
–
t_HD
t_H
Data in hold time
5
–
t_HH
t_HD
HOLD hold time
5
–
t_SH
t_CD
HOLD setup time
5
–
t_CO
t_V
Output valid
–
15
t_HHZ[18]
t_HZ
HOLD to output high Z
–
15
t_HLZ[18]
t_LZ
HOLD to output low Z
–
15
t_OH
t_HO
Output hold time
0
–
t_HZCS[18]
t_DIS
Output disable time
–
25
40 MHz
Min
Max
–
40
11
–
11
–
20
–
10
–
10
–
5
–
5
–
5
–
5
–
–
9
–
15
–
15
0
–
–
20
104 MHz
Min
Max
–
104
4.5
–
4.5
–
20
–
5
–
5
–
4
–
3
–
3
–
3
–
–
8
–
8
–
8
0
–
–
8
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
13. Typical values are at 25 °C, V_CC = V_CC(Typ). Not 100% tested.
14. Current drawn from either V_RTCcap or V_RTCbat when V_CC < V_SWITCH.
15.
IcfaVp_{RaTcCitcoarpm>u0s.t5bVe}
aolrloifwneodctaopcahcaitrogreistoco0n.5neVcftoerdotsocVill^Ra^Tto^Cr^cato^p
pin, the
start.
oscillator
will
start
in
t_OCS
time.
If
a
backup
capacitor
is
connected
and
V_RTCcap
<
0.5
V,
the
16.
Test conditions assume signal transition time of 3 ns
I_OL/I_OH and load capacitance shown in Figure 33.
or
less,
timing
reference
levels
of
V_CC/2,
input
pulse
levels
of
0
to
V_CC(typ),
and
output
loading
of
the
specified
17. Applicable for RTC opcode cycles, address cycles and data out cycles.
18. These parameters are guaranteed by design and are not tested.
Document Number: 001-65268 Rev. *F
Page 33 of 42