CY8CLED16_10 Datasheet, PDF (38/43 Pages) Cypress Semiconductor – EZ-Color™ HB-LED Controller

CY8CLED16
Figure 19. 48-Pin (7x7x1.0 mm) QFN (Sawn)
TOP VIEW
7.00±0.100
48
1
PIN 1 DOT
LASER MARK
37
36
7.00±0.100
12
13
25
24
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MILLIMETERS
SIDE VIEW
0.900±0.100
0.200 REF.
BOTTOM VIEW
0.25
+0.05
-0.07
37
36
5.100 REF
0.50 PITCH
5.100 REF
SOLDERABLE
EXPOSED
PAD
PIN1 ID
R 0.20
1
0.45
5.500±0.100
0.020
+0.025
-0.00
0.40±0.10
25
24
5.500±0.100
12
13
001-13191 *E
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power device.
Thermal Impedances
Table 33. Thermal Impedances per Package
Package
28 SSOP
48 SSOP
48 QFN^[17]
Typical θ_JA ^[16]
94 ^oC/W
69 ^oC/W
28 ^oC/W
Capacitance on Crystal Pins
Table 34. Typical Package Capacitance on Crystal Pins
Package
28 SSOP
48 SSOP
48 QFN
Package Capacitance
2.8 pF
3.3 pF
1.8 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Table 35. Solder Reflow Peak Temperature
Package
28 SSOP
48 SSOP
48 QFN
Minimum Peak
Temperature^[18]
240^oC
220^oC
220^oC
Maximum Peak
Temperature
260^oC
260^oC
260^oC
Notes
16. T_J = T_A + POWER x θ_JA
17. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5^oC with Sn-Pb or 245 ± 5^oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications
Document Number: 001-13105 Rev. *C
Page 38 of 43
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