CY8C23433_13 Datasheet, PDF (36/53 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C23433, CY8C23533
AC Low Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C  T_A  85°C, or 3.0 V to 3.6 V and –40°C  T_A  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 27. AC Low Power Comparator Specifications
Symbol
Description
T_RLPC LPC response time
Min Typ Max Units
Notes
–
–
50
ms ³ 50 mV overdrive comparator
reference set within V_REFLPC
AC Digital Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C  T_A  85°C, or 3.0 V to 3.6 V and –40°C  T_A  85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 28. 5-V and 3.3-V AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS Mode)
CRCPRS
(CRC Mode)
SPIM
Description
Block input clock frequency
V_DD  4.75 V
V_DD < 4.75 V
Input clock frequency
No capture, V_DD 4.75 V
No capture, V_DD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, V_DD  4.75 V
No enable input, V_DD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
V_DD  4.75 V
V_DD < 4.75 V
Input clock frequency
V_DD  4.75 V
V_DD < 4.75 V
Input clock frequency
Input clock frequency
Min
Typ
–
–
–
–
–
–
–
–
–
–
50^[18]
–
–
–
–
–
–
–
50^[18]
–
20
–
50^[18]
–
50^[18]
–
–
–
–
–
–
–
–
–
–
–
–
–
SPIS
Transmitter
Receiver
Input clock (SCLK) frequency
–
–
Width of SS_negated between transmis- 50^[18]
–
sions
Input clock frequency
V_DD  4.75 V, 2 stop bits
V_DD  4.75 V, 1 stop bit
V_DD < 4.75 V
Input clock frequency
–
–
–
–
–
–
V_DD  4.75 V, 2 stop bits
V_DD  4.75 V, 1 stop bit
V_DD < 4.75 V
–
–
–
–
–
–
Max
49.2
24.6
49.2
24.6
24.6
–
49.2
24.6
24.6
–
–
–
–
49.2
24.6
49.2
24.6
24.6
8.2
4.1
–
49.2
24.6
24.6
49.2
24.6
24.6
Unit
Notes
MHz
MHz
MHz
MHz
MHz
ns
MHz
MHz
MHz
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
The SPI serial clock (SCLK) frequency is equal to the input clock
frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
MHz
MHz
MHz
MHz
MHz
MHz
The baud rate is equal to the input clock frequency divided by 8.
The baud rate is equal to the input clock frequency divided by 8.
Note
18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-44369 Rev. *G
Page 36 of 53