CY8C23433_13 Datasheet, PDF (1/53 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C23433, CY8C23533
PSoC^® Programmable System-on-Chip™
Features
■ Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ 8x8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
■ Advanced peripherals (PSoC blocks)
❐ Four Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO Pins
❐ Complex peripherals by combining blocks
❐ High-Speed 8-Bit SAR ADC optimized for motor control
■ Precision, programmable clocking
❐ Internal ±2.5% 24/48 MHz oscillator
❐ High accuracy 24 MHz with optional 32 KHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
■ Flexible on-chip memory
❐ 8K bytes flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Programmable pin configurations
❐ 25 mA Sink, 10 mA source on all GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐ Up to eight analog inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
■ Additional system resources
❐ I²C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
Logic Block Diagram
PSoC CORE
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM Flash 8K
CPUCore (M 8C)
Sleep and
Watchdog
Multiple ClockSources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
1 Row
4 Blocks
ANALOG SYSTEM
Analog
Block Array
2 Columns
4 Blocks
SAR8 ADC
Analog
Ref
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum. ^Decimator
I²C
POR and LVD ^Internal
System Resets
Voltage
Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44369 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 8, 2013