CYP15G0201DXB Datasheet, PDF (32/46 Pages) Cypress Semiconductor – Dual-channel HOTLink II Transceiver

CYP15G0201DXB
CYV15G0201DXB
CYP(V)15G0201DXB AC Characteristics Over the Operating Range (continued)
Parameter
Description
t_RREFDA[34]
Receive Data Access Time from REFCLK (RXCKSEL = LOW)
t_RREFDV
Receive Data Valid Time from REFCLK (RXCKSEL = LOW)
t_REFADV–
Received Data Valid Time to RXCLKA (RXCKSEL = LOW)
t_REFADV+
Received Data Valid Time from RXCLKA (RXCKSEL = LOW)
t_REFCDV–
Received Data Valid Time to RXCLKC (RXCKSEL = LOW)
t_REFCDV+
t_REFRX ^{[29, 31]}
Received Data Valid Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Extracted Received Clock Frequency
Transmit Serial Outputs and TX PLL Characteristics
Min.
Max. Unit
9.5
ns
2.5
ns
10UI – 4.7
ns
0.5
ns
10UI – 4.3
ns
–0.2
ns
–0.02
+0.02 %
t_B
t_RISE[29]
Bit Time
CML Output Rise Time 20% – 80% (CML Test Load)
SPDSEL = HIGH
SPDSEL = MID
5100
50
100
660
ps
270
ps
500
ps
t_FALL[29]
SPDSEL = LOW
180
1000 ps
CML Output Fall Time 80% – 20% (CML Test Load)
SPDSEL = HIGH
50
270
ps
SPDSEL = MID
100
500
ps
t_DJ[29, ^{36, 37, 38]} Deterministic Jitter (peak-peak)
t_RJ[29, ^{35, 37]}
Random Jitter (σ)
t_TXLOCK
Transmit PLL lock to REFCLK
Receive Serial Inputs and CDR PLL Characteristics
t_RXLOCK
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
SPDSEL = LOW
180
1000 ps
IEEE 802.3z
25
ps
IEEE 802.3z
11
ps
200
us
376K
376K
UI^[38]
UI
t_RXUNLOCK
Receive PLL Unlock Rate
t_JTOL[37]
Total Jitter Tolerance
t_DJTOL[37]
Deterministic Jitter Tolerance
Capacitance^[29]
IEEE 802.3z
IEEE 802.3z
46
UI
600
ps
370
ps
Parameter
Description
Test Conditions
Max. Unit
C_INTTL
TTL Input Capacitance
T_A = 25°C, f₀ = 1 MHz, V_CC = 3.3V
7
pF
C_INPECL
PECL input Capacitance
T_A = 25°C, f₀ = 1 MHz, V_CC = 3.3V
4
pF
Notes:
34. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t_RREFDA and set-up
time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW)
could be used to clock the receive data out of the device.
35. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of the differential outputs over the operating range.
36. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range.
37. Total jitter is calculated at an assumed BER of 1E−12. Hence: Total Jitter (t_J) = (t_RJ * 14) + t_DJ.
38. Receiver UI (Unit Interval) is calculated as 1/(f_REF * 20) (when RXRATE = HIGH) or 1/(f_REF * 10) (when RXRATE = LOW) if no data is being received, or 1/(f_REF * 20)
(when RXRATE = HIGH) or 1/(f_REF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t_B.
Document #: 38-02058 Rev. *G
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