CY8C21323_08 Datasheet, PDF (30/37 Pages) Cypress Semiconductor – PSoC® Mixed Signal Array

CY8C21123, CY8C21223, CY8C21323
AC Programming Specifications
Table 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
design guidance only.
Table 34. AC Programming Specifications
Symbol
T_RSCLK
T_FSCLK
T_SSCLK
T_HSCLK
F_SCLK
T_ERASEB
T_WRITE
T_DSCLK3
T_DSCLK2
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min Typ Max Units
Notes
1
–
20
ns
1
–
20
ns
40
–
–
ns
40
–
–
ns
0
–
8
MHz
–
15
–
ms
–
30
–
ms
–
–
50
ns 3.0 ≤ Vdd ≤ 3.6
–
–
70
ns 2.4 ≤ Vdd ≤ 3.0
AC I²C Specifications
Table 35 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T_A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 35. AC Characteristics of the I²C SDA and SCL Pins for Vcc ≥ 3.0V
Symbol
Description
F_SCLI2C
T_HDSTAI2C
T_LOWI2C
T_HIGHI2C
T_SUSTAI2C
T_HDDATI2C
T_SUDATI2C
T_SUSTOI2C
T_BUFI2C
T_SPI2C
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time⁰
Setup Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
Standard Mode
Min
Max
0
100
4.0
–
4.7
–
4.0
–
4.7
–
0
–
250⁰
–⁰
4.0
–
4.7
–
–
–
Fast Mode
Min
Max
0
400
0.6
–
Units
kHz
μs
1.3
0.6
0.6
0
100^a
0.6
1.3
0
–
μs
–
μs
–
μs
–
μs
–⁰
ns⁰
–
μs
–
μs
50
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT ≥ 250 ns must then be met. This automatically
becomes the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output
the next data bit to the SDA line t_rmax + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12022 Rev. *H
Page 30 of 37
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