W245-30 Datasheet, PDF (3/12 Pages) Cypress Semiconductor – Frequency Multiplying, Peak Reducing EMI Solution

W245-30
Table 1. Frequency Configuration (Frequencies in MHz)
Range of Fin
Frequency
Min.
Max.
14
30
14
30
14
30
25
60
25
60
25
60
50
120
50
120
50
120
Reserved
Power Down Hi-Z
Power Down 0
Power Down 1
Multiplier
Settings
OR2 OR1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
Output /
Input
1
2
4
0.5
1
2
0.25
0.5
1
N/A
N/A
N/A
N/A
Range of Fout
Min. Max.
14
30
28
60
56
120
13
30
25
60
50
120
13
30
25
60
50
120
N/A N/A
N/A N/A
N/A N/A
N/A N/A
Required R
Settings
IR2
IR1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
As Set As Set
As Set As Set
As Set As Set
As Set As Set
Modulation & Pow-
er Down Settings
MW2
MW1
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
1
0
1
1
0
0
0
1
Table 2. Modulation Width Selection Table
EMI Reduction
Minimum EMI Control
Suggested Setting
Alternate Setting
Maximum EMI reduction
Modulation Setting
MW2
0
0
1
1
MW1
0
1
0
1
Bandwith Limit Frequencies as a% Value of Fout
MW0 = 0
MW0 = 1
Low
High
Low
High
98.75%
100% 99.375%
100.625
97.5%
100%
98.75
101.25%
95.0%
100%
97.5%
102.5%
90.0%
100%
95%
105%
Overview
The W245-30 product is one of a series of devices in the Cy-
press PREMIS family. The PREMIS family incorporates the
latest advances in PLL spread spectrum frequency synthesiz-
er techniques. By frequency modulating the output with a low
frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Functional Description
The W245-30 uses a phase locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W245-30 the
output frequency is nominally equal to the input frequency.)
The unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pins
MW0:2 as shown in Table 2.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
Document #: 38-07229 Rev. *B
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