W162 Datasheet, PDF (3/7 Pages) Cypress Semiconductor – Spread Aware™, Zero Delay Buffer

W162
Absolute Maximum Ratings^[1]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
V_DD, V_IN
T_STG
T_A
T_B
P_D
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability
Rating
Unit
–0.5 to +7.0
V
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
DC Electrical Characteristics: T_A =0°C to 70°C, V_DD = 3.3V ±10%
Parameter
I_DD
V_IL
V_IH
V_OL
Description
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
V_OH
Output High Voltage
I_IL
Input Low Current
I_IH
Input High Current
Test Condition
Unloaded, 100 MHz
I_OL = 12 mA (-19)
I_OL = 8 mA (-9)
I_OL = 12 mA (-19)
I_OL = 8 mA (-9)
V_IN = 0V
V_IN = V_DD
Min
Typ
2.0
2.4
–500
Max
Unit
40
mA
0.8
V
V
0.4
V
V
µA
10
µA
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f_IN
Input Frequency
15
133
MHz
f_OUT
Output Frequency
15-pF load^[6]
15
133
MHz
t_R
Output Rise Time (-09)^[2] 2.0 to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-19)^[2] 2.0 to 0.8V, 20-pF load
1.5
ns
t_F
Output Fall Time (-09)^[2] 2.0 to 0.8V, 15-pF load
Output Rise Time (-19)^[2] 2.0 to 0.8V, 20-pF load
2
2.5
ns
1.5
ns
t_PD
FBIN to REF Skew^{[3, 4]}
Measured at V_DD/2
150
ps
t_SK
Output to Output Skew
All outputs loaded equally
150
ps
t_D
Duty Cycle
15-pF load^[5]
45
50
55
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
250
ps
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Long input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at V_DD/2 on rising edges.
5. Duty cycle is measured at V_DD/2
6. For the higher drive -19, the load is 20 pF.
Document #: 38-07150 Rev. *A
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