W162 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – Spread Aware™, Zero Delay Buffer

W162
Spread Aware™, Zero Delay Buffer
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Two banks of four outputs, plus the fed back output
• Outputs may be three-stated
• Available in 16-pin SOIC or SSOP package
• Extra strength output drive available (-19 version)
• Internal feedback
Key Specifications
Operating Voltage: ............................................... 3.3V±10%
Operating Range: ................................15 < f_OUT < 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: ............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Block Diagram
Table 1. Input Logic
SEL1
0
0
SEL0
0
1
QA0:3
Three-
State
Active
1
0
Active
1
1
Active
QB0:3
Three-
State
Three-
State
Active
Active
PLL
QFB
Shutdown Active
Active,
Utilized
Shutdown,
Bypassed
Active,
Utilized
Active
Active
Active
Pin Configuration
REF
PLL
MUX
SEL0
SEL1
QFB
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
REF
1
QA0
2
QA1
3
VDD
4
GND
5
QB0
6
QB1
7
SEL1
8
16
QFB
15
QA3
14
QA2
13
VDD
12
GND
11
QB3
10
QB2
9
SEL0
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07150 Rev. *A
Revised December 14, 02