W162 Datasheet, PDF (2/7 Pages) Cypress Semiconductor – Spread Aware™, Zero Delay Buffer

W162
Pin Definitions
Pin Name
REF
QFB
QA0:3
QB0:3
VDD
GND
SEL0:1
Pin No.
1
16
2, 3, 14, 15
6, 7, 10, 11
4, 13
5, 12
9, 8
Pin
Type
I
O
O
O
P
P
I
Pin Description
Reference Input: The output signals QA0:3 through QB0:3 will be synchro-
nized to this signal unless the device is programmed to bypass the PLL.
Feedback Output: This signal is used as the feedback internally to establish
the propagation delay of nearly 0.
Outputs from Bank A: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
Outputs from Bank B: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect all grounds to the common system ground
plane.
Function Select Inputs: Tie to V_DD (HIGH, 1) or GND (LOW, 0) as desired
per Table 1.
Overview
The W162 products are nine-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide eight copies of that same signal out.
Internal feedback is used to maximize the number of output
signals provided in the 16-pin package.
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a
zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchroniza-
tion.
For more details on Spread Spectrum timing technology,
please see the Cypress Application note titled, “EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Functional Description
Logic inputs provide the user the ability to turn off one or both
banks of clocks when not in use, as described in Table 1. Dis-
abling a bank of unused outputs will reduce jitter and power
consumption, and will also reduce the amount of EMI gener-
ated by the W162.
These same inputs allow the user to bypass the PLL entirely
if so desired. When this is done, the device no longer acts as
a zero delay buffer, it simply reverts to a standard nine-output
clock driver.
Document #: 38-07150 Rev. *A
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