CYV15G0404RB Datasheet, PDF (3/26 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink Reclocking Deserializer

PRELIMINARY
CYV15G0404RB
Reclocking Deserializer Path Block Diagram
TRGRATEA
TRGCLKA
x2
SDASEL[2..1]A[1:0]
LDTDEN
INSELA
INA1+
INA1–
INA2+
INA2–
ULCA
SPDSELA
RXPLLPDA
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Recovered Character Clock
10
RXBISTA[1:0]
RXRATEA
Recovered Serial Data
JTAG
Boundary
Scan
Controller
10
10
÷2
= Internal Signal
RESET
TRST
TMS
TCLK
TDI
TDO
LFIA
RXDA[9:0]
BISTSTA
RXCLKA+
RXCLKA–
ROE[2..1]A
RECLKOA
REPDOA
Reclocker
Output PLL
Clock Multiplier A
Character-Rate Clock A
ROE[2..1]A
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
TRGRATEB
TRGCLKB
SDASEL[2..1]B[1:0]
LDTDEN
INSELB
INB1+
INB1–
INB2+
INB2–
ULCB
SPDSELB
RXPLLPDB
x2
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
10
10
RXBISTB[1:0]
RXRATEB
Recovered Character Clock
Recovered Serial Data
RECLKOB
REPDOB
Reclocker
Output PLL
Clock Multiplier B
Character-Rate Clock B
ROE[2..1]B
10
÷2
LFIB
RXDB[9:0]
BISTSTB
RXCLKB+
RXCLKB–
ROE[2..1]B
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
Document #: 38-02102 Rev. **
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