CYV15G0404RB Datasheet, PDF (14/26 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink Reclocking Deserializer

PRELIMINARY
CYV15G0404RB
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The
third row of latches for each channel (address numbers 2, 5,
8, and 11) are the dynamic control latches that are associated
with enabling dynamic functions within the device.
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[7:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Static Latch Values
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
There are some latches in the table that have a static value (ie.
1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured
with their corresponding value each time that their associated
latch bank is configured. The latches that have an ‘X’ are don’t
cares and can be configured with any value
dynamic signals. In this case, this feature becomes available
Table 3. Device Configuration and Control Latch Descriptions
Name
RXRATEA
RXRATEB
RXRATEC
RXRATED
Signal Description
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to
select the rate of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKx+ and RXCLKx–.
SDASEL1A[1:0]
SDASEL1B[1:0]
SDASEL1C[1:0]
SDASEL1D[1:0]
SDASEL2A[1:0]
SDASEL2B[1:0]
SDASEL2C[1:0]
SDASEL2D[1:0]
TRGRATEA
TRGRATEB
TRGRATEC
TRGRATED
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
RXBISTA[1:0]
RXBISTB[1:0]
RXBISTC[1:0]
RXBISTD[1:0]
ROE2A
ROE2B
ROE2C
ROE2D
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered
clock operating at the character rate. Data for the associated receive channels should be latched on the
rising edge of RXCLKx+ or falling edge of RXCLKx–.
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the
INx1± Primary Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the
INx2± Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420mV.
Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to
select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx =
0, the associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx
= 1, the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and
SPDSELx = LOW is an invalid state and this combination is reserved.
Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive
PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and
analog circuitry are enabled.
Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch =
11. For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11).
RXBISTx[1:0] selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE
data reception. When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated
channel is set to receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled
and the associated channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are
invalid states.
Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the
ROE2x latch = 0. ROE2x selects if the ROUT2± secondary differential output drivers are enabled or
disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be
transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is
disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce
device power. If both serial drivers for a channel are in this disabled state, the associated internal logic
for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.
Document #: 38-02102 Rev. **
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