CYV15G0404RB Datasheet, PDF (16/26 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink Reclocking Deserializer

PRELIMINARY
CYV15G0404RB
Table 4. Device Control Latch Configuration Table
ADDR Channel Type
DATA7
DATA6
DATA5
DATA4
0
A
S
1
(0000b)
0
X
X
1
A
(0001b)
S SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0]
2
A
D RXBISTA[1] RXPLLPDA RXBISTA[0]
X
(0010b)
3
B
S
1
(0011b)
0
X
X
4
B
(0100b)
S SDASEL2B[1] SDASEL2B[0] SDASEL1B[1] SDASEL1B[0]
5
B
D RXBISTB[1] RXPLLPDB RXBISTB[0]
X
(0101b)
6
C
S
1
(0110b)
0
X
X
7
C
(0111b)
S SDASEL2C[1] SDASEL2C[0] SDASEL1C[1] SDASEL1C[0]
8
C
D RXBISTC[1] RXPLLPDC RXBISTC[0]
X
(1000b)
9
D
S
1
(1001b)
0
X
X
10
D
(1010b)
S SDASEL2D[1] SDASEL2D[0] SDASEL1D[1] SDASEL1D[0]
11
D
D RXBISTD[1] RXPLLPDD RXBISTD[0]
X
(1011b)
12 GLOBAL S
1
(1100b)
0
X
X
13 GLOBAL S SDASEL2GL[1] SDASEL2GL[0] SDASEL1GL[1] SDASEL1GL[0]
(1101b)
14 GLOBAL D RXBISTGL[1] RXPLLPDGL RXBISTGL[0]
X
(1110b)
15 MASK D
D7
D6
D5
D4
(1111b)
DATA3
0
X
ROE2A
0
X
ROE2B
0
X
ROE2C
0
X
ROE2D
0
X
ROE2GL
D3
DATA2
0
DATA1
RXRATEA
DATA0
GLEN0
X
TRGRATEA GLEN1
ROE1A
X
GLEN2
0
RXRATEB GLEN3
X
TRGRATEB GLEN4
ROE1B
X
GLEN5
0
RXRATEC GLEN6
X
TRGRATEC GLEN7
ROE1C
X
GLEN8
0
RXRATED GLEN9
X
TRGRATED GLEN10
ROE1D
X
GLEN11
0
RXRATEGL FGLEN0
X
TRGRATEGL FGLEN1
ROE1GL
X
FGLEN2
D2
D1
D0
Reset
Value
10111111
10101101
10110011
10111111
10101101
10110011
10111111
10101101
10110011
10111111
10101101
10110011
N/A
N/A
N/A
11111111
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
Table 5. Receive BIST Status Bits
{BISTSTx, RXDx[0],
RXDx[1]}
000, 001
010
011
100
101
110
111
Description
Receive BIST Status
(Receive BIST = Enabled)
BIST Data Compare. Character compared correctly.
BIST Last Good. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad. Last Character of BIST sequence detected invalid.
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error. While comparing characters, a mismatch was found in one or more of the character bits.
BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to
enable the LFSR.
Document #: 38-02102 Rev. **
Page 16 of 26