CYP15G0401TB Datasheet, PDF (3/30 Pages) Cypress Semiconductor – Quad HOTLink II™ Transmitter

PRELIMINARY
Transmit Path Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
2
TXCKSEL
TXPERA
SCSEL
TXDA[7:0] 8
Transmit PLL
Clock Multiplier
Character-Rate Clock
Transmit
Mode
12
12
TXOPA
TXCTA[1:0] ²
TXCLKA
TXPERB
HML
TXDB[7:0] 8
TXOPB
TXCTB[1:0] ²
11
11
HML
TXCLKB
TXPERC
TXDC[7:0] 8
TXOPC
TXCTC[1:0] ²
11
11
HML
TXCLKC
TXPERD
TXDD[7:0] 8
TXOPD
TXCTD[1:0]
11
11
HML
TXCLKD
TXRST
PARCTL
Bit-rate Clock
BIST Enable
Latch
4
12
10
12
10
12
10
12
10
JTAG
Boundary
Scan
Controller
Document #: 38-02112 Rev. **
CYP15G0401TB
Output
Enable
Latch
8
TRSTZ
BISTLE
BOE[7:0]
OELE
OUTA1+
OUTA1–
OUTA2+
OUTA2–
OUTB1+
OUTB1–
OUTB2+
OUTB2–
OUTC1+
OUTC1–
OUTC2+
OUTC2–
OUTD1+
OUTD1–
OUTD2+
OUTD2–
TMS
TCLK
TDI
TDO
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