CYP15G0401TB Datasheet, PDF (1/30 Pages) Cypress Semiconductor – Quad HOTLink II™ Transmitter

PRELIMINARY
CYP15G0401TB
Quad HOTLink II™ Transmitter
Features
• Quad transmitter for 195 to 1500 MBaud serial signaling
rate
— Aggregate throughput of 6 GBits/second
• Second-generation HOTLink^® technology
• Compliant to multiple standards
— ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— 8B/10B encoded or 10-bit unencoded data
• Selectable parity check
• Selectable input clocking options
• Synchronous LVTTL parallel interface
• Optional Phase Align Buffer in Transmit Path
• Internal phase-locked loop (PLL) with no external PLL
components
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— fiber-optic modules
— copper cables
— circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low power 1.9W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb free package option available
• 0.25µ BiCMOS technology
Functional Description
The CYP15G0401TB Quad HOTLink II™ Transmitter is a
point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195-to-1500 MBaud
per serial link.
Each transmitter accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. Figure 1 illustrates typical connections
between independent host systems and corresponding
CYP15G0401TB and CYP15G0401RB parts.
As a second-generation HOTLink device, the CYP15G0401TB
extends the HOTLink family with enhanced levels of
integration and faster data rates, while maintaining serial-link
compatibility (data, command, and BIST) with other HOTLink
devices. The transmitters (TX) of the CYP15G0401TB Quad
HOTLink II consist of four byte-wide channels. Each channel
can accept either eight-bit data characters or pre-encoded
10-bit transmission characters. Data characters are passed
from the Transmit Input Register to an embedded 8B/10B
Encoder to improve their serial transmission characteristics.
These encoded characters are then serialized and output from
dual Positive ECL (PECL)-compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock. The integrated 8B/10B Encoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
Serial Link
10
10
Serial Link
10
10
Serial Link
10
10
Serial Link
10
10
Backplane or
Cabled
Connections
Figure 1. HOTLink II System Connections
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02112 Rev. **
Revised February 14, 2005