CY14E108L Datasheet, PDF (3/20 Pages) Cypress Semiconductor – 8 Mbit (1024K x 8/512K x 16) nvSRAM

ADVANCE
CY14E108L, CY14E108N
Pin Definitions
Pin Name IO Type
Description
A₀ – A₁₉
A₀ – A₁₈
DQ0 – DQ7
Input
Input/Output
Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration.
Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE high.
BHE
BLE
V_SS
V_CC
HSB
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Ground Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional).
V_CAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM
to nonvolatile elements.
NC
No Connect No Connect. Do not connect this pin to the die.
Document Number: 001-45524 Rev. *A
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