CY14E108L Datasheet, PDF (11/20 Pages) Cypress Semiconductor – 8 Mbit (1024K x 8/512K x 16) nvSRAM

ADVANCE
CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2: CE and OE Controlled^{[10, 21, 23]}
ADDRESS
CE
t_RC
t_LZCE
t_ACE
t_PD
t_HZCE
OE
BHE , BLE
DQ (DATA OUT)
t_DOE
tLZOE
t_DBE
tLZBE
t HZOE
t_HZCE
t_HZBE
DATA VALID
t_PU
ACTIVE
ICC
STANDBY
ADDRESS
CE
WE
BHE , BLE
DATA IN
DATA OUT
Figure 7. SRAM Write Cycle #1: WE Controlled^{[13, 21, 22, 23]}
tWC
tSA
tSCE
tAW
tPWE
tHA
tBW
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Notes
22. CE or WE must be >V_IH during address transitions.
23. BHE and BLE are applicable for x16 configuration only.
Document Number: 001-45524 Rev. *A
Page 11 of 20
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