CY8C36_13 Datasheet, PDF (29/129 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C36 Family Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIO×, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (VCCA) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the
VDDIO pins must have capacitors connected as shown in
Figure 6-4. The two VCCD pins must be shorted together, with
as short a trace as possible, and connected to a 1-µF ±10% ×5R
capacitor. The power system also contains a sleep regulator, an
I²C regulator, and a hibernate regulator.
VDDIO2
Figure 6-4. PSoC Power System
1 µF
VDDD
0.1 µF
0.1 µF
VDDIO0
I/O Supply
I/O Supply VDDIO0
I2C
Regulator
0.1 µF
Digital
Domain
VSSB
Digital
Regulators
Sleep
Regulator
Analog
Regulator
VDDA
VCCA
Analog
Domain
VSSA
VDDA
1 µF
0.1µF
Hibernate
Regulator
I/O Supply
0.1 µF
VDDIO1
0.1 µF
VDDD
I/O Supply
0.1 µF
VDDIO3
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-8 on page 10.
You can power the device in internally regulated mode, where the voltage applied to the V_DDx pins is as high as 5.5 V, and the internal
regulators provide the core voltages. In this mode, do not apply power to the V_CCx pins, and do not tie the V_DDx pins to the V_CCx
pins.
You can also power the device in externally regulated mode, that is, by directly powering the V_CCD and V_CCA pins. In this configuration,
the V_DDD pins should be shorted to the V_CCD pins and the V_DDA pin should be shorted to the V_CCA pin. The allowed supply range in
this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be
disabled to reduce power consumption.
Document Number: 001-53413 Rev. *Q
Page 29 of 129