CY8C36_13 Datasheet, PDF (20/129 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C36 Family Datasheet
Interrupts form Fixed
function blocks, DMA and
UDBs
Interrupts 0 to 31
from UDBs
Interrupts 0 to 31
from Fixed
Function Blocks
Interrupts 0 to
31 from DMA
Interrupt
routing logic
to select 32
sources
Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupt Enable/
Disable, PEND and
POST logic
0
Highest Priority
1
IRQ
Individual
Enable Disable
bits
8 Level
Priority
decoder
for all
interrupts
0 to 31 ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Table 4-8. Interrupt Vector Table
#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Fixed Function
LVD
Cache/ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I²C
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
Global Enable
disable bit
DMA
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
Lowest Priority
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
Document Number: 001-53413 Rev. *Q
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