CY8C21634 Datasheet, PDF (29/42 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 32. 5V and 3.3V AC Digital Block Specifications
Function
Description
Min
All
Functions
Timer
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
50^a
Maximum Frequency, No Capture
–
Maximum Frequency, With or Without Capture –
Counter Enable Pulse Width
50
Maximum Frequency, No Enable Input
–
Maximum Frequency, Enable Input
–
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
Synchronous Restart Mode
50
Disable Mode
50
Maximum Frequency
–
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
–
(CRC
Mode)
SPIM
Maximum Input Clock Frequency
–
SPIS
Maximum Input Clock Frequency
–
Width of SS_ Negated Between Transmissions 50
Transmitter Maximum Input Clock Frequency
–
Receiver
Maximum Input Clock Frequency with Vdd ≥ –
4.75V, 2 Stop Bits
Maximum Input Clock Frequency
–
Maximum Input Clock Frequency with Vdd ≥ –
4.75V, 2 Stop Bits
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
49.2
24.6
–
49.2
24.6
–
49.2
24.6
–
–
–
49.2
49.2
24.6
8.2
4.1
–
24.6
49.2
24.6
49.2
Units
MHz
MHz
ns
MHz
MHz
ns
MHz
MHz
Notes
4.75V < Vdd < 5.25V.
3.0V < Vdd < 4.75V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
ns
ns
ns
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
MHz
MHz
MHz
ns
MHz
MHz
MHz
MHz
Maximum data rate at 4.1 MHz
due to 2 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12025 Rev. *L
Page 29 of 42
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