CY8C21634 Datasheet, PDF (15/42 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Mixed-Signal Array
Technical Reference Manual.
Register Conventions
The register conventions specific to this section are listed in Table 8.
Table 8. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into
two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user
is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and must not be accessed.
Table 9. Register Map 0 Table: User Space
PRT0DR
00
RW
40
PRT0IE
01
RW
41
PRT0GS
02
RW
42
PRT0DM2
03
RW
43
PRT1DR
04
RW
44
PRT1IE
05
RW
45
PRT1GS
06
RW
46
PRT1DM2
07
RW
47
PRT2DR
08
RW
48
PRT2IE
09
RW
49
PRT2GS
0A
RW
4A
PRT2DM2
0B
RW
4B
PRT3DR
0C
RW
4C
PRT3IE
0D
RW
4D
PRT3GS
0E
RW
4E
PRT3DM2
0F
RW
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
Blank fields are Reserved and must not be accessed.
Document Number: 38-12025 Rev. *L
ASE10CR0
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
# Access is bit specific.
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
RW
D1
RW
D2
D3
RW
D4
RW
D5
RW
D6
RW
D7
#
D8
RW
D9
#
DA
RW
DB
RW
DC
DD
RW
DE
RW
DF
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